Lab 12 of 15 · rank 11
Inputs CLK and EN. Outputs Q0–Q3 (Q0 the lowest bit), starting at 0. On each rising edge of CLK, if EN is 1, Q goes up by one, wrapping from 15 to 0. If EN is 0, Q holds.
Turn logic into a permanent, verifiable part.
A chain of half adders adds EN to Q (bit 0 gets EN, each next bit gets the carry below). Four DFFs clocked by CLK store the sums.
Par is 20 NAND and 8 LATCH. Using more still passes here. To etch it as a verified die that mines, keep it within 72 NAND-equivalent (a LATCH counts 2): the verifier refuses bigger designs, so padding can't buy mining weight.
Turn this circuit into a verified die you own. It burns 0 NAND. Get materials at the Foundry.