Lab 13 of 15 · rank 12

Wafer-4: a 4-bit CPU

Inputs OP1 OP0 (instruction), D0–D3 (data), CLK. Outputs A0–A3 (accumulator), C (carry), Z (zero). On each CLK rising edge: 00 LOAD A←D, 01 ADD A←A+D with C = carry-out, 10 AND A←A&D, 11 XOR A←A^D. C is 0 for every instruction but ADD; Z is 1 when the new A is 0. A, C and Z are all registers that update on the clock edge.

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1
Build itPorts named OP1, OP0, CLK, D0, D1, D2, D3 and A0, A1, A2, A3, C, Z
2
Pass the truth table124 rows checked
3
Etch it (optional)a verified die in your project

⊼

Cellsclick one, then click the canvas

Build your die

Turn logic into a permanent, verifiable part.

NAND used0 / par 117

LATCH used0 / par 12

Pick a cell on the left, click to place it · drag from an output pin to an input pin to wire · click a wire to remove it · click a cell to rename it

→ Y=0

What it should do

OP1 OP0 CLK D0 D1 D2 D3A0 A1 A2 A3 C Z

LOAD 0, LOAD 0 → A=0 Z0 0 0 0 0 1

LOAD 0, LOAD 3 → A=31 1 0 0 0 0

LOAD 0, LOAD 7 → A=71 1 1 0 0 0

LOAD 0, LOAD 8 → A=80 0 0 1 0 0

LOAD 0, LOAD 15 → A=151 1 1 1 0 0

LOAD 0, ADD 0 → A=0 Z0 0 0 0 0 1

LOAD 0, ADD 3 → A=31 1 0 0 0 0

LOAD 0, ADD 7 → A=71 1 1 0 0 0

LOAD 0, ADD 8 → A=80 0 0 1 0 0

LOAD 0, ADD 15 → A=151 1 1 1 0 0

LOAD 0, AND 0 → A=0 Z0 0 0 0 0 1

LOAD 0, AND 3 → A=0 Z0 0 0 0 0 1

LOAD 0, AND 7 → A=0 Z0 0 0 0 0 1

LOAD 0, AND 8 → A=0 Z0 0 0 0 0 1

LOAD 0, AND 15 → A=0 Z0 0 0 0 0 1

LOAD 0, XOR 0 → A=0 Z0 0 0 0 0 1

LOAD 0, XOR 3 → A=31 1 0 0 0 0

LOAD 0, XOR 7 → A=71 1 1 0 0 0

LOAD 0, XOR 8 → A=80 0 0 1 0 0

LOAD 0, XOR 15 → A=151 1 1 1 0 0

LOAD 1, LOAD 0 → A=0 Z0 0 0 0 0 1

LOAD 1, LOAD 3 → A=31 1 0 0 0 0

LOAD 1, LOAD 7 → A=71 1 1 0 0 0

LOAD 1, LOAD 8 → A=80 0 0 1 0 0

LOAD 1, LOAD 15 → A=151 1 1 1 0 0

LOAD 1, ADD 0 → A=11 0 0 0 0 0

LOAD 1, ADD 3 → A=40 0 1 0 0 0

LOAD 1, ADD 7 → A=80 0 0 1 0 0

LOAD 1, ADD 8 → A=91 0 0 1 0 0

LOAD 1, ADD 15 → A=0 C Z0 0 0 0 1 1

LOAD 1, AND 0 → A=0 Z0 0 0 0 0 1

LOAD 1, AND 3 → A=11 0 0 0 0 0

LOAD 1, AND 7 → A=11 0 0 0 0 0

LOAD 1, AND 8 → A=0 Z0 0 0 0 0 1

LOAD 1, AND 15 → A=11 0 0 0 0 0

LOAD 1, XOR 0 → A=11 0 0 0 0 0

LOAD 1, XOR 3 → A=20 1 0 0 0 0

LOAD 1, XOR 7 → A=60 1 1 0 0 0

LOAD 1, XOR 8 → A=91 0 0 1 0 0

LOAD 1, XOR 15 → A=140 1 1 1 0 0

…and 84 more rows, all checked.

Stuck?

Per bit: an adder (HA for bit 0, FA above it), an AND and an XOR; two MUXes pick on OP0 and a third on OP1; a DFF clocked by CLK holds the bit. C = cout3 AND (NOT OP1 AND OP0) into a DFF; Z = NOR of the next A bits into a DFF.

Par is 117 NAND and 12 LATCH. Using more still passes here. To etch it as a verified die that mines, keep it within 282 NAND-equivalent (a LATCH counts 2): the verifier refuses bigger designs, so padding can't buy mining weight.

Etch it as a die (optional)

Turn this circuit into a verified die you own. It burns 0 NAND. Get materials at the Foundry.

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