Lab 9 of 15 · rank 08
Inputs A0–A3 and B0–B3 (A0/B0 the lowest bit). Outputs S0–S3 and C (the carry out). S = A + B, and C = 1 when the sum doesn't fit in 4 bits.
Turn logic into a permanent, verifiable part.
…and 216 more rows, all checked.
A half adder on bit 0, then three full adders, each taking the carry of the one below.
Par is 32 NAND. Using more still passes here. To etch it as a verified die that mines, keep it within 64 NAND-equivalent (a LATCH counts 2): the verifier refuses bigger designs, so padding can't buy mining weight.
Turn this circuit into a verified die you own. It burns 0 NAND. Get materials at the Foundry.