Lab 4 of 15 · rank 03

Half adder

Inputs A, B. Outputs S (sum) and C (carry). S is XOR, C is AND.

Learn first

Adding two bits gives a sum bit and a carry bit: 1 + 1 = 10.

In binary, 1 + 1 isn't 2 — it's 10 (one-zero): the sum bit is 0 and a 1 carries over to the next column, just like 7 + 5 = 12 carries a 1 in decimal.

The sum bit is XOR of the inputs (lab 3). The carry is AND of the inputs (lab 2). Put the two side by side and you have a half adder.

Try this

Build XOR from A and B for output S. Build AND from the same A and B for output C. Two outputs, one circuit. Check: 1 + 1 gives S=0, C=1.

1
Build itPorts named A, B and S, C
2
Pass the truth table4 rows checked
3
Etch it (optional)a verified die in your project

⊼

Cellsclick one, then click the canvas

Build your die

Turn logic into a permanent, verifiable part.

NAND used0 / par 5

LATCH used0 / par 0

Pick a cell on the left, click to place it · drag from an output pin to an input pin to wire · click a wire to remove it · click a cell to rename it

→ Y=0

What it should do

A BS C

0 00 0

0 11 0

1 01 0

1 10 1

Stuck?

XOR for S, AND for C. Or a single HA macro.

Par is 5 NAND. Using more still passes here. To etch it as a verified die that mines, keep it within 10 NAND-equivalent (a LATCH counts 2): the verifier refuses bigger designs, so padding can't buy mining weight.

Etch it as a die (optional)

Turn this circuit into a verified die you own. It burns 0 NAND. Get materials at the Foundry.

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